Cisco Hiring ASIC Engineer New Grad 2027 | Bangalore

Cisco is hiring ASIC Engineers (New Grad) in Bangalore for its Silicon One team, and the posting is only for 2027 graduates. It covers two tracks: ASIC Physical Design Engineer and ASIC Design and Verification Engineer. The page is marked as an evergreen requisition, which means it stays open for applications over time.

Job Overview

About the team

Cisco Silicon One designs networking silicon used in the company's core products. These chips go into high-density, high-speed switches and routers for AI networking, data centres, campus networks and service provider networks. The posting says the physical design team in Bangalore works on state-of-the-art chips in advanced process nodes (sub 5, 3 and 2 nm).

The two tracks

ASIC Physical Design Engineer

You drive the backend flow from RTL to GDSII: hierarchical floor planning, place and route, timing closure, power integrity, static timing verification, physical verification and equivalence checks, with focus on performance and die size.

What the posting asks for: strong digital design, CMOS technology, VLSI principles, timing and power fundamentals; comfort with the full RTL to GDSII flow from logic synthesis and floorplanning through placement, clock tree synthesis, routing, static timing analysis and signoff; knowledge of setup and hold timing, clock skew, congestion, IR drop, electromigration, DRC, LVS, PVT corners and SDC constraints; and solid scripting skills to automate workflows.

ASIC Design and Verification Engineer

You design and verify multimillion gate ASICs.

What the posting asks for: knowledge of hardware design and test and verification environments built with an object-oriented framework in UVM, based on coursework in data structures, algorithms and design patterns, with languages such as SystemVerilog HDL, C, C++ and Python.

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Eligibility Criteria

• Graduation year 2027 only. Earlier batches should not apply to this requisition.
• A strong foundation in engineering and digital design. The posting does not name specific degree branches, so check the official page, though the skills listed point to electronics, electrical or computer engineering.

Skills Required (common to both)

• Solid engineering and digital design fundamentals
• Technical problem solving
• Ability to manage multiple tasks toward long-term goals
• Strong relationships across a wider team
• Excellent verbal and written communication
• A team-player attitude, with the ability to contribute individually

Salary and Benefits

Cisco does not publish a salary in this posting. Do not trust numbers on other sites. Ask about the compensation structure with the recruiter after you are shortlisted. The page describes Cisco as an innovation-focused company, but those are company statements, not job terms.

Is this job right for you?

It suits you if:

• You enjoy digital design, VLSI and timing analysis, and have done a course project in Verilog, SystemVerilog or physical design tools.
• You like scripting (Python, Tcl or shell) to automate repetitive flows.
• You are in your final year or about to graduate in 2027.

You may want to skip it if:

• You are from a batch other than 2027.
• You prefer software roles. This is chip design work.
• You do not have any exposure to hardware description languages.

A day in the life

Our reading of the duties. A physical design engineer runs the flow on a block, checks timing reports, finds paths that fail setup or hold, and fixes them by changing placement, buffering or constraints. A verification engineer writes UVM testbenches, builds tests for new features, runs regressions and debugs failures in waveforms. Both roles involve many scripts, reviews and conversations with the architecture and RTL teams.

7-day preparation plan (general guidance)

1. Day 1: Revise CMOS basics: inverter, delay, power.
2. Day 2: Revise timing: setup, hold, clock skew, slack.
3. Day 3: Learn the ASIC flow end to end: RTL, synthesis, floorplan, place and route, CTS, STA, signoff.
4. Day 4: Practise SystemVerilog: classes, interfaces, constrained randomisation.
5. Day 5: Read about UVM structure: driver, monitor, sequencer, scoreboard.
6. Day 6: Write a small Python or Tcl script that parses a timing report.
7. Day 7: Mock interview and review your final-year project.

Likely interview questions (general guidance)

• What is setup and hold time, and how do you fix a violation? Hint: explain both, then talk about buffers, sizing and clock skew.
• What causes IR drop and electromigration? Hint: resistance in the power grid and high current density in wires.
• Explain the difference between synthesis and place and route.
• What is a testbench, and what makes verification coverage useful?
• Write a function to reverse a string in Python or C++.

Career path and what to learn next

Physical design and verification roles lead to senior engineer, technical lead and architect tracks in semiconductor companies. Strong next skills are advanced timing closure, low-power design, formal verification and scripting. Compared with a software engineering job (see Cisco hiring Software Engineer in Bangalore), this path needs specialised VLSI knowledge and tool experience.

Application checklist

• Highlight VLSI coursework, HDL projects and tools you used. See resume tips for freshers.
• Keep your academic documents ready. See documents required for job applications.
• Put your graduation year (2027) clearly on your resume.
• Use only the official Cisco careers link below.

Scam and safety reminders

Cisco itself warns about fraudulent recruiters. Genuine communication will come from official channels, and Cisco will not ask you to pay. Read how to identify fake job offers.

Common mistakes freshers make with chip design applications

These are general observations, not Cisco's official advice.

• Listing tools you have only watched a video about. Interviewers in VLSI roles tend to probe the exact flow you ran. If you list a place and route tool, be ready to explain each step you personally did and what the timing report looked like.
• Ignoring fundamentals for tool names. Many candidates memorise tool commands but cannot explain why a hold violation is fixed by adding delay. Strong basics beat a long tool list.
• Skipping scripting. The posting says scripting is essential for physical design. Even a small Python script that reads a report and prints the worst paths shows the right habit.
• Weak project descriptions. Say what the block was, how many gates or cells it had, which constraints you set and what result you reached. A number is more convincing than an adjective.
• Missing the batch rule. The posting is for 2027 graduates only. Applying from another batch will not help and may waste your time on this requisition.

If you are unsure which track suits you, read both descriptions again. Choose physical design if you enjoy timing, layout and flow automation. Choose design and verification if you enjoy writing testbenches and finding bugs with code. You can mention interest in both, but show depth in one.

How to Apply

Open the official Cisco careers page for Job ID 2027556 and apply with your resume. Check the page for the latest status because evergreen listings can close.

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